BCLR=0, FRDY=0, BVAL=0
D1FIFO Port Control Register
| DTLN | Receive Data LengthIndicates the length of the receive data. |
| FRDY | FIFO Port Ready 0 (0): FIFO port access is disabled. 1 (1): FIFO port access is enabled. |
| BCLR | CPU Buffer Clear 0 (0): Invalid 1 (1): Clears the buffer memory on the CPU side |
| BVAL | Buffer Memory Valid Flag 0 (0): Invalid 1 (1): Writing ended |